1. Field of Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a contactless mask programmable read-only memory (Mask ROM).
2. Description of Related Art
Read-only memory (ROM) is a type of non-volatile memory, which can retain data as disconnected from power supply, and therefore is used to store permanent data like booting data of computer systems.
In order to simplify the fabricating processes and to increase the integration of ROM devices, various ROM structures are proposed based on shared diffusion and integration of the coding process and the contact process. Some conventional ROM devices are described below.
FIG. 1 illustrates a top view of a contact ROM in the prior art.
Referring to FIG. 1, the contact ROM 100 comprises rows and columns of MOS-type memory cells, wherein two adjacent memory cells in the same column constitute a cell pair 102 that is isolated by field isolation 104. The memory cells in the same row are controlled by a word line 106, and the memory cells in the same column are located under a bit line 108. The two memory cells in a cell pair 102 share a source 110 between the two drains 112 thereof, while the sources 110 of the cell pairs 102 in the same row are electrically connected to a ground line 114. In the contact ROM 100, a plurality of contacts 116 are selectively formed on the drains 112 of the memory cells as data codes, wherein the contacts in the same column are connected to a bit line 108.
During a reading operation of the contact ROM, the selected word line 106 is biased to high level. If the drain 112 of the selected memory cell has a contact 116 thereon electrically connecting with the selected bit line 108, a current can be conducted from the selected bit line 108 to the ground line 114 connecting with the source 110 of the selected memory cell. Otherwise, no current is detected. In other words, the data is stored as a contact pattern. However, since the field isolation 104 is formed between two rows of cell pairs 102 and contacts 116 are formed on the drains 112, the area of the memory array is large and the device integration is low.
FIG. 2 illustrates a top view of an implant programmable ROM in the prior art.
Referring to FIG. 2, the implant programmable ROM 200 comprises rows and columns of MOS-type memory cells 201. The memory cells in the same row are controlled by a word line 202 and every two rows of memory cells 201 are coupled to a ground line 204, while two columns of memory cells 201 are separated by isolation 203. A memory cell 201 shares a source 206 with one adjacent memory cell in the same column, and shares a drain 208 with the other adjacent memory cell in the same column. The sources 206 of the memory cells 201 in the same row are connected to a ground line 204, and the drains 208 of the memory cells 201 in the same column are electrically connected to a bit line 210 via contacts 212. The implant programmable ROM 200 is programmed by selectively implanting ions into the channel regions under the word lines 202 to make the selected channel regions 214 have a higher threshold voltage (VT). During the reading operation of the implant programmable ROM, the selected word line 202 is biased to high level. If the channel region of the selected memory cell 201 is not implanted, the channel can be switched on and an On-current can be detected, otherwise the channel cannot be switched on and the channel current is extremely small.
As compared with the contact ROM 100 in FIG. 1, the implant programmable ROM 200 is more compact because the isolation between rows of memory cells is omitted and a drain 208 is shared by two memory cells 201 like a source 206. However, since an additional mask is needed for selectively implanting the channel regions of the memory cells 201, the fabricating process is more complex. Moreover, in consideration of the lateral area necessary for forming the contacts 212, the degree of area reduction of the drain region 208 is limited and the memory array cannot be further miniaturized.
FIG. 3 illustrates a top view of a Metal ROM in the prior art.
Referring to FIG. 3, the Metal ROM 300 has a NAND (NOT AND) structure and comprises rows and columns of MOS-type memory cells. The memory cells in the same row are controlled by a word line 302 and four continuous memory cells in the same column are grouped as a memory string 304. In a memory string 304, the diffusion 305 of one terminal memory cell is electrically connected to a ground line 306, and the diffusion 305 of the other terminal memory cell is coupled to a bank select transistor 308. The bank select transistor 308 is coupled to a bit line 320 parallel to the memory string 304 via a contact 322. The source and the drain of a memory cell, i.e., the two diffusions 305 of a memory cell, are both shared by adjacent cells.
The Metal ROM is programmed by selectively forming local interconnects 326 each connecting the two diffusions 305 of a selected memory cell. If a memory cell has a local interconnect 326 formed thereon like memory cell C1 does, the memory cell is always electrically conductible and acts like a depletion-type MOS devices, otherwise the memory cell is in the enhanced mode like memory cell C2 is. During a reading operation, the selected bit line 320 is coupled to a certain voltage level, the selected word line 302 is coupled to low level, and the unselected word lines 302 and the gate 340 of the bank select transistor 308 are coupled to high level. Thus, the bank select transistor 308 and all of the unselected memory cells in the same memory string 304 are switched on. Consequently, if the selected memory cell has a local interconnect 326 formed thereon, a current can be conducted through it and can be detected, otherwise no current is detected. The Metal ROM is more compact than the contact ROM, but the memory area in the Metal ROM cannot be further reduced because local interconnects must be formed on the diffusions 305 (sources and drains).